VLSI Implementation of a Cost-Efficient Loeffler DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

This paper presents a low-cost and high-quality, hardware-oriented, two-dimensional discrete cosine transform (2-D DCT) signal analyzer for image video encoders. In order to reduce memory requirement improve quality, novel Loeffler DCT based on coordinate rotation digital computer (CORDIC) technique is proposed. addition, the proposed algorithm realized by recursive CORDIC architecture instead of an unfolded with approximated scale factors. design, fully pipelined developed efficiently increase operating frequency throughput, factors are implemented using four hardware-sharing machines complexity reduction. Thus, computational can be decreased significantly only 0.01 dB loss deviated from optimal quality DCT. Experimental results show that 2-D spectral not achieved superior average peak signal–noise ratio (PSNR) compared previous CORDIC-DCT algorithms but also designed cost-efficient very large integration (VLSI) implementation. The design was UMC 0.18-μm CMOS process synthesized gate count 8.04 k core area 75,100 μm2. Its 100 MHz power consumption 4.17 mW. Moreover, this work had at least 64.1% reduction saved 22.5% in designs.